1. Field of the Invention
The present invention relates to a method of evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories.
2. Discussion of the Related Art
The reliability of nonvolatile memories of the aforementioned types is known to depend on the quality of the dielectric layers, which term is intended here to mean both the gate oxide and the dielectric layer interposed between the two polycrystalline silicon layers defining the control gate and floating gate regions and generally referred to as the "interpoly dielectric".
Evaluation of the gate oxide is especially important in the case of flash-EEPROM memories, the cells of which, as shown in the FIG. 1 cross section of a flash-EEPROM cell 100, present a thinner gate oxide layer as compared with those of EPROM memories. More specifically, FIG.1 shows a P type substrate 1; N type drain and source regions 2 and 3; a gate oxide layer 4; a floating gate region 5; an interpoly dielectric layer 6; a control gate region 7; and a protective oxide layer 8.
The gate oxide layer of flash-EEPROM memories presents a thickness of roughly 110 A (as compared with roughly 200 A for EPROM cells) so as to enable erasure of the flash cells by Fowler-Nordheim tunneling current at voltages leaving the cell itself undamaged. Passage of the tunneling current through the gate oxide, which may be defined as the tunnel oxide by virtue of performing the same functions as the tunnel oxide of EEPROM cells, thus enables electron removal from the floating gate.
In view of its functions, therefore, the flash cell tunnel oxide must be of guaranteed reliability both in terms of resistance to the electrical stress typical of EPROM memories, and in terms of erasure characteristics. Hence, the importance of an effective, reliable method of evaluating the quality of the tunnel oxide.
At present, this is done using tunnel oxide MOS capacitors made specially for the purpose, and wherein the area or perimeter of the capacitors (depending on the side of the cell being considered) is equivalent to that of the arrays used; and the test method itself consists in subjecting the capacitors to voltage or current stress, and evaluating the electric field or total charge at breakdown of the capacitor. At times, the entire current/voltage characteristic obtainable under stress is evaluated.
The above diagnosis and evaluation method, however, presents several drawbacks affecting its precision. To begin with, it has not yet been established beyond all doubt whether a correlation exists between the breakdown charge or electric field values and the presence of defective-oxide cells in arrays manufactured in the same process.
Moreover, not even with the current/voltage characteristics obtained with the above known method is it possible to detect oxide defects when the degree of deficiency of the oxide is such as to affect only some of the cells in the overall array. In fact, the currents responsible for the variation in the threshold of defective-gate-oxide cells, particularly at deficiency levels of a few defects per cm , are rarely measurable, due to the limitation posed by the noise level of the measuring instruments, and the presence at the same time of the gate current of the overall area of the capacitor. This latter factor becomes increasingly more stringent as the deficiency levels for detection get lower, thus requiring the measurement of increasingly higher-area capacitors and so impairing the measuring sensitivity of the method.
Even using known redundancy methods, the presence of even a small number of defective cells may result in failure of the memory. Consequently, as process efficiency and memory reliability depend on the degree of deficiency involved, it is essential that measuring instruments be made available that are capable of detecting even very low deficiency levels.
In the case of new-generation devices, wherein the total area of the interpoly dielectric tends to increase, thus resulting in a reduction in deficiency (expressed in terms of defects per cm.sup.2), the quality of the interpoly dielectric also becomes increasingly important.
Current techniques employing straightforward test structures for evaluating the quality of the interpoly dielectric are similar to and present basically the same limitations as the gate oxide techniques, and generally provide for measuring the current-voltage characteristics, and the electric field or charge at breakdown of (large-area or large-perimeter) capacitors with a dielectric identical to the interpoly dielectric. Such a method provides solely for detecting defects with a dominant current/voltage characteristic as compared with that of the overall capacitor, and fails to detect less evident defects which could affect the charge state of nonvolatile memory cells.
More accurate information may be obtained by testing the device itself, which, however, involves a considerable increase in fabrication and test time as compared with straightforward test structures.
It is an object of the present invention to provide a method of detecting defective cells due to poor quality of the gate oxide or interpoly dielectric, and which provides for improved diagnostic performance as compared with known methods and structures currently employed for the purpose.